CMOS memory cell with gate oxide of both NMOS and PMOS transistors as tunneling window for program and erase
US5596524A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Apr 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS memory cell including a PMOS transistor and an NMOS transistor having a common floating gate with a gate oxide region of both the NMOS and PMOS transistors providing a tunneling window for program and erase. The PMOS and NMOS transistors of the CMOS memory cell are biased so that only the PMOS transistor is utilized during programming and only the NMOS transistor is utilized during erase to prevent depletion of the substrate beneath the tunneling oxide regions. The CMOS memory cell further includes a separate PMOS pass transistor for supplying a program voltage to the source of the PMOS transistor underlying the common floating gate, so that an NMOS threshold does not have to be added to the program voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.