First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus
US5596729A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Mar 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved arbitration scheme including multiple arbiters for arbitrating access to a PCI bus and an ISA bus. The PCI arbiter controls access to the PCI bus by various bus masters, including the CPU/main memory subsystem, various other PCI bus masters, an enhanced DMA or EDMA controller, and an 8237-compatible DMA controller. The PCI arbiter utilizes a modified LRU arbitration scheme. Further, an SD arbiter exists to arbitrate access to the data portion (SD) of the ISA bus. The various devices that may request the SD bus include the EDMA controller, a PCI master in a PCI-to-ISA operation, the DMA controller, an ISA bus master, and the refresh controller. The SD arbiter assigns the highest priority to the PCI bus, followed by the refresh controller, EDMA controller, and DMA controller or ISA bus masters. The DMA controller includes an arbiter for arbitrating between its channels. The DMA arbiter further includes logic to ensure that the DMA controller or ISA bus master relinquishes control of the ISA bus after one arbitration cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.