Robert A. Lester
53Patents
24h-index
61Co-inventors
91Inventor score
Filing activity: Mar 3, 1995 → Feb 13, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6286083A | Computer system with adaptive memory arbitration scheme | Physics | 176 | Expired |
| US6715116B2 | Memory data verify operation | Physics | 142 | Expired |
| US7010652B2 | Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency | Physics | 116 | Expired |
| US6785785B2 | Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency | Physics | 114 | Expired |
| US6363439B1 | System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system | Physics | 106 | Expired |
| US6766469B2 | Hot-replace of memory | Physics | 103 | Expired |
| US5905509A | Accelerated Graphics Port two level Gart cache having distributed first level caches | Physics | 97 | Expired |
| US6832340B2 | Real-time hardware memory scrubbing | Physics | 64 | Expired |
| US6160562A | System and method for aligning an initial cache line of data read from local memory by an input/output device | Physics | 63 | Expired |
| US6078338A | Accelerated graphics port programmable memory access arbiter | Physics | 59 | Expired |
| US5596729A | First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus | Physics | 58 | Expired |
| US6854070B2 | Hot-upgrade/hot-add memory | Physics | 56 | Expired |
| US5999198A | Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device | Physics | 54 | Expired |
| US5936640A | Accelerated graphics port memory mapped status and control registers | Physics | 53 | Expired |
| US6202101A | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Physics | 43 | Expired |
| US5949436A | Accelerated graphics port multiple entry gart cache allocation system and method | Physics | 42 | Expired |
| US6247102A | Computer system employing memory controller and bridge interface permitting concurrent operation | Physics | 40 | Expired |
| US6823424B2 | Rebuild bus utilization | Physics | 38 | Expired |
| US5923859A | Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus | Physics | 34 | Expired |
| US7320086B2 | Error indication in a raid memory system | Physics | 31 | Expired |
| US6470429B1 | System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops | Physics | 31 | Expired |
| US5914727A | Valid flag for disabling allocation of accelerated graphics port memory space | Electricity | 29 | Expired |
| US5990914A | Generating an error signal when accessing an invalid memory page | Physics | 27 | Expired |
| US6785835B2 | Raid memory | Physics | 26 | Expired |
| US5999743A | System and method for dynamically allocating accelerated graphics port memory space | Physics | 23 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.