Single clock bus transfers during burst and non-burst cycles
US5596731A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1995 |
| Grant date | Jan 21, 1997 |
| Priority date | — |
| Expiry date | Apr 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single block bus transfer (SCBT) protocol is implemented, in an exemplary embodiment, in a computer system that includes an .times.86 microprocessor, system logic, and an external memory subsystem including L2 cache and system DRAM, intercoupled by a 586 bus architecture. The microprocessor's bus interface unit (BIU) includes SCBT logic that generates internal effective BRDY# and the effective KEN# signals from either (a) L2.sub.-- HIT from the L2 cache, or (b) BRDY# or KEN# from the system logic. The effective KEN# signal is used for convert a potentially cacheable read into a burst fill cycle. The exemplary L2 cache is able to perform address decode and cache look-up in time to return L2 HIT to the processor during the ADS# clock with sufficient timing margin to permit the processor to complete the bus transfer (either not burst bus cycle, or the first bus transfer of a burst cycle) in that clock and set up for a next bus transfer in the next clock. The BIU uses a forced deadclock mechanism to prevent a single clock bus transfer from being followed in the next clock by a next bus transfer if the result would be consecutive read and write cycles (thereby avoiding device driver c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.