Method of making stacked electrical device having regions of electrical isolation and electrical connection on a given stack level
US5602051A · kind A · utility
15Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1995 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Oct 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
An improved method for isolating electrical conductors which are positioned over each other is disclosed. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. The method involves forming a recess in the upper surface of the lower conductor, and then at least partially filling the recess with an oxide-type material. This method is particularly valuable in the construction of stacked capacitor cells. Cells prepared using this technique also form part of this invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.