Method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device, and column redundancy integrated circuitry
US5602786A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1995 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Feb 16, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/789
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device with columns of memory elements grouped together to form portions of a bi-dimensional array of memory elements. The column redundancy circuitry comprises a plurality of non-volatile memory registers wherein each register is associated with a respective redundancy column of redundancy memory elements and each register is programmable to store an address of a defective column and an identifying code for identifying the portion of the bi-dimensional array to which the defective column belongs. When being programmed, each non-volatile memory register is supplied with column address signals and with a first subset of row address signals. The column address signals carry the address of a defective column and the first subset of row address signals carry the identifying code. One signal of a second subset of the row address signals is used to select one non-volatile memory register among the plurality of registers such that the defective column address and the identifying code carried by the column address signals and by the first subset of the row address signals ar…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.