Method for decreasing time penalty resulting from a cache miss in a multi-level cache system
US5603004A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 1994 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Feb 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache system buffers data stored in a main memory and utilized by a processor. The cache system includes a first cache, a second cache, a first transfer channel, a second transfer channel and a third transfer channel. The first cache is fully associative. The second cache is directly mapped. The first transfer channel transfers data lines from the main memory to the first cache. The second transfer channel transfers data lines from the first cache to the second cache. The third transfer channel transfers data lines from the second cache to the main memory. Accesses of data lines from the first cache and the second cache are performed in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.