Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
US5603005A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 1994 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Dec 27, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for identifying obsolete data within cache memory in a multiprocessor architecture. This is accomplished while still providing the advantages of having cache resources dedicated to individual instruction processors as well as shared intermediate level cache modules. The technique provides the band pass and attendant performance advantages of an essentially point-to-point architecture without all of the added hardware of a centralized master system storage controller. Further, unlike a strictly point-to-point architecture, the present invention is readily expandable to service a large number of multiprocessors without burdening each of the multiprocessors with the corresponding increase in interface and connection costs of a strictly point-to-point architecture. This simplifies the design of the multiprocessor elements and also allows a system to be expanded to include more or less multiprocessors by simply including a modified XBAR interface. In a strictly point-to-point architecture, the multiprocessors may have to be modified to expanding a system because the interfacing circuitry associated therewith is contained therein. The present invention further has …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.