Mitchell A. Bauman
54Patents
27h-index
47Co-inventors
88Inventor score
Filing activity: Dec 3, 1984 → Nov 8, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5678026A | Multi-processor data processing system with control for granting multiple storage locks in parallel and parallel lock priority and second level cache priority queues | Physics | 107 | Expired |
| US6480927B1 | High-performance modular memory system with crossbar connections | Physics | 101 | Expired |
| US5603005A | Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed | Physics | 93 | Expired |
| US6178466A | System for maximizing bandpass on an interface directly coupling two units where the interface has independently operative data and address interconnections, and computer sysem employing same. | Physics | 87 | Expired |
| US6594785B1 | System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitions | Physics | 87 | Expired |
| US6799252B1 | High-performance modular memory system with crossbar connections | Physics | 85 | Expired |
| US5875472A | Address conflict detection system employing address indirection for use in a high-speed multi-processor system | Physics | 72 | Expired |
| US7047322B1 | System and method for performing conflict resolution and flow control in a multiprocessor system | Physics | 69 | Expired |
| US6434641B1 | System for reducing the number of requests presented to a main memory in a memory storage system employing a directory-based caching scheme | Physics | 60 | Expired |
| US6014709A | Message flow protocol for avoiding deadlocks | Physics | 57 | Expired |
| US5875462A | Multi-processor data processing system with multiple second level caches mapable to all of addressable memory | Physics | 52 | Expired |
| US6052760A | Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks | Physics | 51 | Expired |
| US6189078A | System and method for increasing data transfer throughput for cache purge transactions using multiple data response indicators to maintain processor consistency | Physics | 51 | Expired |
| US5960455A | Scalable cross bar type storage controller | Physics | 49 | Expired |
| US6415364B1 | High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems | Physics | 49 | Expired |
| US6381715B1 | System and method for performing parallel initialization and testing of multiple memory banks and interfaces in a shared memory module | Physics | 45 | Expired |
| US5680571A | Multi-processor data processing system with multiple, separate instruction and operand second level caches | Physics | 42 | Expired |
| US6167489A | System and method for bypassing supervisory memory intervention for data transfers between devices having local memories | Physics | 41 | Expired |
| US6981106B1 | System and method for accelerating ownership within a directory-based memory system | Physics | 39 | Expired |
| US5832304A | Memory queue with adjustable priority and conflict detection | Physics | 38 | Expired |
| US6122711A | Method of and apparatus for store-in second level cache flush | Physics | 35 | Expired |
| US6356991B1 | Programmable address translation system | Physics | 34 | Expired |
| US6182112A | Method of and apparatus for bandwidth control of transfers via a bi-directional interface | Physics | 33 | Expired |
| US7343515B1 | System and method for performing error recovery in a data processing system having multiple processing partitions | Physics | 31 | Expired |
| US4596977A | Dual slope analog to digital converter with out-of-range reset | Electricity | 29 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.