Test access architecture for testing of circuits modules at an intermediate node within an integrated circuit chip
US5604432A · kind A · utility
26Cited by
7References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 5, 1993 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | Nov 5, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318544
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test access architecture is implemented which allows embedded testing of reusable modules and their interconnections with each other and with primary system inputs and outputs, utilizing reusable test vectors regardless of the configuration of the integrated circuit. Also provided is a method and apparatus for controlling and observing signals within the logic of a module, using the same test access architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.