Time linearity measurement using a frequency locked, dual sequencer automatic test system
US5604751A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 1995 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | Nov 9, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3191
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for automatically testing digital electronic circuits and performing time measurements whereby a digital signal having a frequency f1 is sampled at a rate equal to f2. The sampling frequency f2 is either slightly less than or slightly greater than f1. As a result, the digital signal is sampled at either a slightly later position in time or a slightly earlier position in time during each successive period of the digital signal. After the entire interval of interest on the digital signal has been sampled, either the number of logical high data samples or the number of logical low data samples is determined. Finally, the number of data samples is multiplied by the effective time period between data samples. In this way, pulse widths on digital signals can be measured with both high resolution and good linearity. This method of time measurement may also be used to calibrate an electronic circuit tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.