Memory system reset circuit
US5604755A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 1995 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | Nov 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0796
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reset circuit for resetting a memory system following a radiation event includes an error detect circuit for producing an error signal in response to detection of an uncorrectable error in the systems memory arrays, and includes a control circuit for selectively resetting at least select portions of the memory system in response to the error detect signal. All or portions of the memory arrays can be reset by the control circuit, and complete or selective latch reset, or selective power recycling are provided. In one embodiment, the control circuit provides latch reset in response to the error detect signal so as to reset the memory latches without recycling power, and in another embodiment, the control circuit selectively cycles power to independent memory zones of the system to reset only those zones whose memory array is identified as having an uncorrectable error. Preferably, the control circuit, and perhaps the detect circuit, are radiation hardened to further ensure dependable operation of the reset circuit following a radiation event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.