Single array address translator with segment and page invalidate ability and method of operation
US5604879A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 23, 1996 |
| Grant date | Feb 18, 1997 |
| Priority date | — |
| Expiry date | May 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CAM/SRAM structure (44) performs address translations that are compatible with a segmentation/paging addressing scheme yet require only a single look-up step. Each entry in the effective-to-real-address-translator (ERAT) has two CAM fields (ESID, EPI) that independently compare an input segment identifier and an input page identifier to a stored segment identifier and a stored page identifier, respectively. The ERAT outputs a stored real address field (DATA) associated with a stored segment-stored page pair if both comparisons are equivalent. The ERAT can invalidate stored translations on the basis of segment or page granularity by requiring either a segment or a page CAM field match, respectively, during an invalidate operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.