Brad B. Beavers
4Patents
4h-index
9Co-inventors
36Inventor score
Filing activity: Apr 4, 1994 → May 23, 1996
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5604879A | Single array address translator with segment and page invalidate ability and method of operation | Physics | 27 | Expired |
| US5682495A | Fully associative address translation buffer having separate segment and page invalidation | Physics | 26 | Expired |
| US5835946A | High performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizations | Physics | 21 | Expired |
| US5530822A | Address translator and method of operation | Physics | 13 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.