Non-delay based address transition detector (ATD)
US5606269A · kind A · utility
9Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1995 |
| Grant date | Feb 25, 1997 |
| Priority date | — |
| Expiry date | Oct 26, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for detecting an input signal, the circuit having an input node and an output node, includes a first latch having a set input coupled to the input node, for detecting falling transitions at the input node. A second latch having a set input coupled to the input node, detects rising transitions at the input node. A first logic device, responsive to outputs of the first and second latches, detects that an input signal has been received at both the first and second latches. A second logic device, responsive to a complement output of both the first and second latches, resets both the first and second latches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.