Method and apparatus for streamlined concurrent testing of electrical circuits
US5606566A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 6, 1995 |
| Grant date | Feb 25, 1997 |
| Priority date | — |
| Expiry date | Sep 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electrical circuit includes a serial scan test architecture having first and second separate serial scan paths respectively coupled to first and second portions of the electrical circuit for permitting data to be scanned through the electrical circuit for testing thereof. The first serial scan path is operatively enabled while the second serial scan path is also operatively enabled, thereby permitting concurrent scan testing of the first and second portions of the electrical circuit. Test signals are transferred between the first serial scan path and the first portion of the electrical circuit and between the second serial scan path and the second portion of the electrical circuit while serial test data is being transferred in first and second continuous serial data streams through the first and second serial scan paths, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.