Method and apparatus for performing serial and parallel scan testing on an integrated circuit
US5606568A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1995 |
| Grant date | Feb 25, 1997 |
| Priority date | — |
| Expiry date | Nov 30, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31908
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit test apparatus according to an exemplary embodiment includes a first memory section configured to store processor procedures and a second memory section configured to simultaneously store parallel integrated circuit test vectors and serial integrated circuit test vectors. A processor is coupled to the first memory section and to the second memory section. The processor is configured to execute the processor procedures to simultaneously manipulate the parallel integrated circuit test vectors and the serial integrated circuit test vectors located in the second memory to test an integrated circuit. Advantages of the invention include the ability to simultaneously store serial and parallel test vectors and to test a device under test (DUT) with simultaneous serial and parallel test vectors. The combination of serial and parallel test vectors increases performance and efficiency of the test apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.