Branch prediction and resolution apparatus for a superscalar computer processor
US5606676A · kind A · utility
69Cited by
14References
13Claims
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Key dates
| Filing date | Feb 9, 1995 |
| Grant date | Feb 25, 1997 |
| Priority date | — |
| Expiry date | Feb 9, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be resolved in one of two distinct pipeline stages, and a method is provided for handling branches that are resolved in either of the pipeline stages. A branch verification method is provided that verifies that the architecturally correct instructions are in the decode and execution stages. Furthermore, two sets of prefetch buffers are provided to allow branch prediction when multiple clock decoding is required by a multi-clock instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.