Method for fabricating a DRAM cell with a T shaped storage capacitor
US5607874A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1996 |
| Grant date | Mar 4, 1997 |
| Priority date | — |
| Expiry date | Feb 2, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
Two embodiments of a method are described for fabricating a DRAM cell having a T or Y shaped capacitor connected to a MOS transistor with source and drain regions. In a first embodiment, the method comprises using two masks to form a cylindrical hole partial through the insulating layer and a concentric contact hole over the source. A first conductive layer is formed over the first insulating layer, at least completely filling the trench and filling the contact hole. In a key step, the first polysilicon layer is chemically mechanically polished thereby forming a T shaped storage electrode. Next, a capacitor dielectric layer and a top electrode are sequentially formed over at least the T shaped storage electrode. The second embodiment form the contact hole and trench as described above. A conformal first conductive layer is formed over the first insulating layer, filling the contact hole and covering the sidewalls and bottom of the trench, but not filling the trench. A dielectric layer is formed over the first conductive layer at least fills the trench. The dielectric layer and the first conductive layer are chemically mechanically polished forming the Y shaped electrode. Next, a ca…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.