Method of fabricating multilevel interconnections in a semiconductor integrated circuit
US5607880A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1993 |
| Grant date | Mar 4, 1997 |
| Priority date | — |
| Expiry date | Apr 28, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a fabrication method of multilevel interconnections for semiconductor integrated circuits. Aluminium wiring lines are formed on a first silicon oxide film overlying a silicon substrate. A second silicon oxide film is grown by a plasma chemical vapor deposition on the wiring lines and the first silicon oxide film for a specific surface treatment of either an etching with use of fluorine compounds or an ion-implantation of fluorine compounds. A third silicon oxide film is grown on the second silicon oxide film by an atmospheric pressure chemical vapor deposition with use of organic silicon compounds and an oxygen including ozone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.