Flash memory with improved erasability and its circuitry
US5608670A · kind A · utility
43Cited by
6References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 1995 |
| Grant date | Mar 4, 1997 |
| Priority date | — |
| Expiry date | May 8, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.