Fast parity generator using complement pass-transistor logic
US5608741A · kind A · utility
2Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1993 |
| Grant date | Mar 4, 1997 |
| Priority date | — |
| Expiry date | Nov 23, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a fast parity bit generator using 4-bit XOR cells implemented using complement pass-transistor logic. For 2.sup.2n inputs, where n is an arbitrary positive integer, the parity bit is generated in n stages using only ##EQU1## 4-bit XOR cells. For 2.sup.2n+1 inputs, where n is an arbitrary positive integer, the parity bit is generated using ##EQU2## 4-bit XOR cells disposed in n rows and one 2-bit XOR cell disposed in the last row. The speed of operation of the XOR cells is further enhanced by using NMOS transistor logic within the XOR cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.