Dual latency status and coherency reporting for a multiprocessing system
US5608878A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 3, 1994 |
| Grant date | Mar 4, 1997 |
| Priority date | — |
| Expiry date | Oct 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessing system utilizes a bus protocol having two response windows. The first response window is at a fixed latency from the transmission of a bus request and/or address, while the second response window, utilized for coherency reporting, is placed a configurable number of clock cycles after the bus request and address to allow for longer access, or snoop, times to perform a cache directory look-up within other bus devices. The first response window reports error or flow control and error status. Furthermore, a method had been described, which implements the reporting of response information in a flexible and high performance manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.