Semiconductor integrated circuit device having excellent dual polarity overvoltage protection characteristics
US5610426A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1995 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | Jul 21, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A protective circuit that can maintain effectiveness when excess voltages of both polarities are applied is placed between the input terminal of an internal CMOS inverter and an input pad. The protective circuit includes a protective resistor, a P-channel MOSFET and an N-channel MOSFET. The N-channel MOSFET is placed between a connecting line and a ground terminal with the gate terminal of the MOSFET connected to the connecting line. The P-channel MOSFET is placed between the connecting line and the ground terminal with the gate terminal of the MOSFET connected to the connecting line. The P-channel MOSFET releases excess negative voltage from the outside using ON-state current and the N-channel MOSFET releases excess positive voltage from the outside using ON-state current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.