Patent · US Expired

Testing method for semiconductor circuit levels

US5610531A · kind A · utility

0Cited by

11References

13Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Werner Weber · Munich, DE
Siegmar Koeppe · Laatzen, DE
Helmut Klose · Munich, DE
Holger Huebner · Neustadt an der Aisch, DE

Key dates

Filing date	Jan 6, 1995
Grant date	Mar 11, 1997
Priority date	—
Expiry date	Jan 6, 2015

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A function test is implemented for an individual circuit level (1) that is provided for vertical integration in a semiconductor component. Stacks of circuit levels respectively provided over or under this circuit level in the finished component are simulated as test heads (2, 3). These test heads are provided with terminal contacts for reversible contacting. The circuit level (1) under test is connected to these test heads (2, 3) during the function test, and the test heads are removed after the test.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.