Method and apparatus for independently resetting processors and cache controllers in multiple processor systems
US5611078A · kind A · utility
5Cited by
3References
8Claims
0Family size
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Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Mar 11, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/177
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for independently resetting primary and secondary processors 20 and 120 respectively under program control in a multiprocessor, cache memory system. Processors 20 and 120 are reset without causing cache memory controllers 24 and 124 to reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.