Method of manufacturing a DRAM having peripheral circuitry in which source drain interconnection contact of a MOS transistor is made small by utilizing a pad layer
US5612241A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1995 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Oct 31, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A MOS transistor included in a peripheral circuit of a DRAM has conductive layers for interconnection on respective surfaces of a pair of source.multidot.drain regions. The source.multidot.drain interconnection layers are electrically connected to the source.multidot.drain regions through the conductive layers. One of the pair of conductive layers is formed in the same step as a bit line of a memory cell, by the same material as the bit line. The other one of the pair of conductive layers is formed in the same step as a storage node of a capacitor of the memory cell, by using the same material as the storage node. The pair of conductive layers prevent direct connection between the source.multidot.drain interconnection layer and the source.multidot.drain regions, so that reduction in size of the source.multidot.drain regions can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.