Method for manufacturing semiconductor substrate having buck transistor and SOI transistor areas
US5612246A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 1995 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Oct 27, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/911
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor substrate structure wherein a comprising the steps of defining bulk transistor and SOI transistor areas, the bulk transistor area disposed on a lower single crystalline silicon layer, and the SOI transistor area diposed on an upper single crystalline silicon layer. The method characterized in that a spacer is formed on a portion of the bulk transistor area which covers a sidewall of the SOI transistor area, a first conductive well is formed in the lower single crystalline silicon layer and a well oxide layer is formed over the first conductive well region, a second conductive well is formed in the lower single crystalline silicon layer between the SOI transistor layer and the first conductive well, and the first conductive well is rediffused.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.