Jong-Hyon Ahn
33Patents
11h-index
30Co-inventors
71Inventor score
Filing activity: Oct 27, 1995 → Mar 5, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7585734B2 | Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby | Electricity | 39 | Active |
| US6163074A | Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein | Electricity | 24 | Expired |
| US6765255B2 | Semiconductor device having metal-insulator-metal capacitor and fabrication method thereof | Electricity | 20 | Expired |
| US6300233A | Method of making a fuse in a semiconductor device | Electricity | 19 | Expired |
| US7361565B2 | Method of forming a metal gate in a semiconductor device | Electricity | 16 | Expired |
| US6552438B2 | Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same | Electricity | 16 | Expired |
| US7045896B2 | Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer | Electricity | 16 | Expired |
| US6175145A | Method of making a fuse in a semiconductor device and a semiconductor device having a fuse | Electricity | 14 | Expired |
| US6074940A | Method of making a fuse in a semiconductor device and a semiconductor device having a fuse | Emerging Cross-Sectional Technologies | 13 | Expired |
| US6548862B2 | Structure of semiconductor device and method for manufacturing the same | Electricity | 12 | Expired |
| US6465337B1 | Methods of fabricating integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein | Electricity | 12 | Expired |
| US7008835B2 | Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance | Electricity | 9 | Expired |
| US6232189A | Manufacturing method of semiconductor device | Electricity | 8 | Expired |
| US6768199B2 | Flip chip type semiconductor device and method of fabricating the same | Electricity | 8 | Expired |
| US5612246A | Method for manufacturing semiconductor substrate having buck transistor and SOI transistor areas | Emerging Cross-Sectional Technologies | 6 | Expired |
| US7486543B2 | Asymmetrical SRAM device and method of manufacturing the same | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6960785B2 | MOSFET and method of fabricating the same | Electricity | 4 | Expired |
| US7696051B2 | Method of fabricating a MOSFET having doped epitaxially grown source/drain region on recessed substrate | Electricity | 4 | Active |
| US7288848B2 | Overlay mark for measuring and correcting alignment errors | Electricity | 3 | Expired |
| US6764910B2 | Structure of semiconductor device and method for manufacturing the same | Electricity | 3 | Expired |
| US6335567B1 | Semiconductor device having stress reducing laminate and method for manufacturing the same | Emerging Cross-Sectional Technologies | 3 | Expired |
| US7557415B2 | Trench isolation type semiconductor device and related method of manufacture | Electricity | 2 | Active |
| US6482662B1 | Semiconductor device fabricating method | Emerging Cross-Sectional Technologies | 2 | Expired |
| US6285540A | Semiconductor device having a fuse | Emerging Cross-Sectional Technologies | 2 | Expired |
| US7332400B2 | Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance | Electricity | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.