Hybrid pattern self-testing of integrated circuits
US5612963A · kind A · utility
68Cited by
9References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Mar 18, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A hybrid random pattern self-test approach is employed in an on-chip fashion to provide desired test signals to circuits on the chip. A simplified weighting circuit is shown to be effective even when only a single bit from a linear feedback shift register is employed for random signal generation. The reduction in linear feedback shift register size and associated weighting circuitry enables the apparatus to be much more readily usable in an on-product configuration thus resulting in significant initial and subsequent test circuit advantages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.