Method of fabricating low leakage SOI integrated circuits
US5614433A · kind A · utility
26Cited by
12References
5Claims
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Key dates
| Filing date | Dec 18, 1995 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Dec 18, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/15
Abstract
An SOI integrated circuit contains Al implanted below the channel areas of NFETs and has a positive substrate bias, the magnitude of the substrate bias and the implant dose being set such that the bias suppresses backside leakage in the PFETs and the implant dose suppresses leakage in the NFEts in spite of the bias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.