Semiconductor integrated circuit device having power reduction mechanism
US5614847A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1994 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Aug 24, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/213
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.