Non-volatile ferroelectric memory device with leakage preventing function
US5615144A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 1995 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Aug 4, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile ferroelectric memory device includes a plurality of memory cells provided in a matrix manner, each of which comprises a transistor having a gate and source and drain regions formed in a semiconductor region, and a ferroelectric capacitor having first and second electrodes and a ferroelectric layer interposed between the first and second electrodes. The second electrode is connected to one of the source and drain regions of the transistor. The memory device further includes a plurality of pairs of bit lines, each of the bit lines of each of the pairs being connected to the other of the source and drain regions of the transistor of each memory cell in a column of the plurality of memory cells, a plurality of word lines each of which is connected to the gate of the transistor of each memory cell in a row of the plurality of memory cells, a plate potential section for generating a first predetermined potential intermediate between a reference potential and a high DC voltage and supplying the first potential to the first electrode of each of the plurality of memory cells, a well potential section for generating a second predetermined potential lower than the first potenti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.