Latched row decoder for a random access memory
US5615164A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Mar 25, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latched row decoder for a Random Access Memory (RAM). The Decoder includes a set-reset latch that is set when addressed and remains set until reset by a PRE signal; address select logic; a reset device; and gated word line drives. The latch, when set, enables four word line drivers that are driven individually depending on two row address bits. During test, latched decoders may be selected sequentially and not reset, leaving drivers enabled until a test is complete. Thus some or all word lines may be driven simultaneously during test. A RAM including the latched decoder of the present invention has a normal random access mode and at least 4 test modes. The test modes are: Long t.sub.RAS word line disturb mode; toggled word line disturb mode; transfer gate stress mode; and a stress test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.