Flat panel display in which low-voltage row and column address signals control a much higher pixel activation voltage
US5616991A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1995 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Sep 19, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S315/07
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
This invention is directed to an improvement of a field emission display architecture in which low-voltage row and column address signals control a much higher pixel activation voltage. Instead of using a pair of series-coupled transistors in the emitter node grounding path as in the original architecture (one of which is gated by a column signal and the other of which is gated by a row signal), only a single transistor is utilized in the emitter node grounding path, thus eliminating an intermediate node between the two transistors that was responsible for unwanted emissions under certain operating conditions. In a preferred embodiment of the invention, a current regulating resistor is placed in the grounding path in series with the primary grounding transistor, with the resistor being directly coupled to ground. Additionally, for the preferred embodiment of the invention, the gate of the grounding transistor is coupled via a second field-effect transistor to either a row signal or a column signal. In the case where the gate of the first transistor is coupled to a row signal, the gate of the second transistor is coupled to a column signal. Likewise, where the gate of the first tran…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.