Ferroelectric memory and method for controlling operation of the same
US5617349A · kind A · utility
30Cited by
3References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 4, 1996 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Jan 4, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory includes a circuit for temporarily controlling a parasitic capacitance of a pair of data signal lines to an optimum value when data is read out from a memory cell, for the purpose of minimizing a variation of the voltage on the pair of data signal lines caused by factor other than the current caused due to the polarization of the ferroelectric capacitor. Thus, a voltage not smaller than the coercive voltage can be applied between the opposing electrodes of the ferroelectric capacitor, with the result that a sufficient read-out signal voltage can be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.