Semiconductor device having redundancy circuit
US5617365A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 1995 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Sep 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the memory array is divided into memory mats. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there are provided, address comparing circuits each of which storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address, and selection circuitry including logical OR gates for replacing a defective bit line by a spare bit line in accordance with the result of the comparison. Each of the address comparing circuits has stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.