Interface protocol for testing of a cache memory
US5617534A · kind A · utility
9Cited by
12References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 1996 |
| Grant date | Apr 1, 1997 |
| Priority date | — |
| Expiry date | Jan 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a microprocessor and an external cache memory coupled to the microprocessor. The cache memory includes a memory array and an apparatus for initiating a routine to test the integrity of the memory array in response to a signal asserted by the microprocessor. The apparatus generates a two-bit status signal coupled to the microprocessor for communicating IDLE, ACTIVE, PASS and FAIL states of the test routine. The apparatus initiates the test routine a predetermined of number clock cycles after the assertion of the signal provided by the microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.