Wafer edge sealing
US5618380A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1995 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Dec 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/16
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method and process for reducing edge-related defects. The present invention comprises the steps of calibrating multiple process units such that the multiple process units are equally referenced with respect to an edge of a semiconductor wafer. The calibrated multiple process units are then utilized to precisely control respective termination distances of deposited substrate layers with respect to the edge of the semiconductor wafer. Furthermore, the deposited substrate layers are selectively stacked in manner which prevents semiconductor wafer edge-related defects. In so doing, the present claimed invention increases semiconductor device yields.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.