III-V semiconductor gate structure and method of manufacture
US5619064A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 1996 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Jan 16, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/113
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.