Memory system having internal state monitoring circuit
US5619461A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 28, 1995 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Jul 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having a test mode which can be used to access signals internally generated by the system during its operation. The signals accessible in the test mode are not available to a standard user of the system, but can be used by a memory chip designer to determine the cause of a device failure. The memory system includes a test signal switch which is used to route one of a multitude of internal signals to an input/output (I/O) pad where the information can be accessed by a chip designer. In order to access the internal signals, the memory system is first placed into a test mode, which acts to shut off the data paths used for reading the output of the sense amplifier included as part of the data read path or for reading the contents of the status register. A signal specifying a particular test signal of interest is then input. Decode logic is used to verify the coded input signal and control the multiplexer to route a specified internal signal through the switch to the I/O pad. By operating the memory system and monitoring the selected signal or data, a chip designer can isolate the cause of a device failure and investigate solutions to the problem without the need for mic…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.