Two-stage memory refresh circuit
US5619468A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1995 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Dec 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing refresh circuit refreshes a timed circuit in a functionally equivalent manner, whether the timing refresh circuit is operated at a high frequency or a low frequency. The two-stage timing refresh circuit includes a counter and combinational logic, in combination, connected between a refresh timing signal generator and a control circuit. The counter is incremented for each refresh timing signal and decremented for each refresh cycle realized by the control circuit. The combinational logic converts the counter count to a refresh signal by generating a refresh request to the control circuit whenever a count is pending in the counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.