Delay line separator for data bus
US5619541A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1995 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Feb 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the chock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 2 -nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal. The pre-filter generates 20-nanosecond pulses, rather than 10-nanosecond pulses, to ensure that the pulses successfully propagate the entire length of the delay line, despite the presence of significant dispersion within each delay element. Additional circuits are tapped into the delay elements, as…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.