Methods for fabricating integrated circuits including openings to transistor regions

US5620919A · kind A · utility

Assignee

• Paradigm Technology, Inc. · US

Inventors

• Norman Godinho · Los Altos Hills, US
• Frank T. Lee · Monte Sereno, US
• Hsiang-Wen Chen · Cupertino, US
• Richard F. Motta · Los Altos, US
• Juine-Kai Tsang · Palo Alto, US
• Joseph Tzou · Belmont, US
• Jai-Man Baik · San Jose, US
• Ting-Pwu Yen · Fremont, US

Key dates

• Filing date: Mar 30, 1995
• Grant date: Apr 15, 1997
• Expiry date: Mar 30, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.