Method for fabricating CMOS device having low and high resistance portions and wire formed from a single gate polysilicon
US5620922A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Mar 17, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/857
Abstract
A method for fabricating a semiconductor device having a high-resistance polysilicon and low-resistance polysilicon on the surface of a substrate comprises forming a gate oxide film on the substrate, forming a polysilicon film on the gate oxide film, and simultaneously forming a resistance, a wire, and a gate electrode from the polysilicon film by etching using a resist as a mask. Impurities are introduced into the polysilicon for controlling a resistance value thereof to form the high-resistance polysilicon resistance through ion implantation. Impurities are also introduced into the polysilicon to form the low-resistance polysilicon wire through ion implantation. N-type impurities are introduced into the gate electrode of a PMOS transistor and the source and drain regions of the PMOS transistor through ion implantation. P-type impurities are introduced into the gate electrode of an NMOS transistor and the source and drain regions of the NMOS transistor through ion implantation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.