Column redundancy circuit and method of semiconductor memory device
US5621691A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Aug 24, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column redundancy circuit and method of a semiconductor memory device. The column redundancy circuit comprises a programming element for programming a repair column address; a comparing element for comparing the programmed repair column address with a column address inputted from outside to thereby generate a redundancy enable control signal according to result of the comparison; a decoding element for decoding the repair column address signal to thereby generate a decoding signal; and a redundancy column select element for compounding the decoding signal and a data input signal to thereby enable a redundancy column select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.