SRAM with simplified architecture for use with pipelined data
US5621695A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 17, 1995 |
| Grant date | Apr 15, 1997 |
| Priority date | — |
| Expiry date | Jul 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed high capacity SRAM having a density of 256K bits or larger. Individual complementary memory cell pairs are arranged in memory blocks and are directly accessed during write and read operations by input/output circuitry having an input buffer, write driver circuits, sense amplifiers, an output buffer and an output register. Data is read from individual memory blocks using a pipelined read data mode in which data accessed by a row, column and block address during a first cycle is stored in an output (pipeline) register at the beginning of the next cycle. In one embodiment all components of the data input/output circuits are located remotely from the memory blocks and paired data lines are used. In an alternate embodiment, the input buffer, a pipeline register and output buffer components of the data input/output circuits are remotely located, and these components are coupled via single data lines and multiplexers to local write drive and sense amplifier circuits located closely adjacent the individual memory blocks. The SRAM is capable of comparable performance to a divided word line SRAM using modular architecture, but has a much simpler design requiring less area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.