Inventor · Palo Alto, CA, US

Thinh Tran

27Patents
7h-index
16Co-inventors
66Inventor score

Filing activity: Apr 17, 1995 → Dec 21, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US7142477B1 Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses Physics 47 Expired
US5493530A Ram with pre-input register logic Physics 17 Expired
US5621695A SRAM with simplified architecture for use with pipelined data Physics 14 Expired
US5864252A Synchronous circuit with improved clock to data output access time Physics 12 Expired
US7269772B1 Method and apparatus for built-in self-test (BIST) of integrated circuit device Physics 12 Expired
US7728619B1 Circuit and method for cascading programmable impedance matching in a multi-chip system Electricity 10 Active
US8149643B2 Memory device and method Physics 9 Active
US7535772B1 Configurable data path architecture and clocking scheme Physics 7 Active
US7403446B1 Single late-write for standard synchronous SRAMs Physics 7 Expired
US7684257B1 Area efficient and fast static random access memory circuit and method Physics 6 Active
US8527802B1 Memory device data latency circuits and methods Physics 6 Active
US7196925B1 Memory array with current limiting device for preventing particle induced latch-up Physics 6 Expired
US8705310B2 Access methods and circuits for memory devices having multiple banks Physics 4 Active
US8464145B2 Serial interface devices, systems and methods Physics 3 Active
US6167321A Interface module with protection circuit and method of protecting an interface Physics 3 Expired
US8040164B2 Circuits and methods for programming integrated circuit input and output impedances Electricity 3 Active
US8095747B2 Memory system and method Physics 2 Active
US8675434B1 High speed time interleaved sense amplifier circuits, methods and memory devices incorporating the same Physics 2 Active
US7719908B1 Memory having read disturb test mode Physics 1 Active
US9666255B2 Access methods and circuits for memory devices having multiple banks Physics 1 Active
US11211107B1 Magnetic memory read circuit and calibration method therefor Physics 1 Active
US9455027B1 Power management system for high traffic integrated circuit Physics 0 Active
US8358557B2 Memory device and method Physics 0 Active
US11854591B2 Magnetic memory read circuit and calibration method therefor Physics 0 Active
US8873264B1 Data forwarding circuits and methods for memory devices with write latency Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.