Method for manufacturing a semiconductor memory cell and a polysilicon load resistor of the semiconductor memory cell
US5622884A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 1996 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | May 30, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
A method is provided for manufacturing a polysilicon load resistor of a semiconductor memory cell. The semiconductor memory cell is formed with at least one transistor and has a semiconductor substrate with a gate dielectric layer on a portion thereof, and a gate electrode layer over the gate dielectric layer. The method includes the steps of: (a) depositing a insulating layer over the gate electrode layer and the remaining portion of the semiconductor substrate around the gate electrode and gate dielectric layers; (b) depositing a polysilicon layer over the insulating layer; (c) implanting ions in the polysilicon layer so as to adjust resistance thereof; (d) etching the polysilicon layer so as to form a high resistance load resistor; (e) etching the insulating layer so as to expose a portion of the gate electrode layer; and (f) forming a metal contact at two ends of the load resistor, one of the metal contacts being located on the exposed portion of the gate electrode so as to establish electrical connection between the gate electrode layer and the load resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.