Field programmable gate array with write-port enabled memory
US5623217A · kind A · utility
9Cited by
8References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1996 |
| Grant date | Apr 22, 1997 |
| Priority date | — |
| Expiry date | Feb 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable gate array includes programmable function units (PFUs) that may function as either a logic block or a random access memory (RAM). Each PFU has a write-port enable input when the PFUs are being used as user RAM units. In addition, each PFU includes a write-strobe input. The write operation is accomplished when both the write-port enable input and the write-strobe input are active. This technique allows a reduction of logic gates and control signal conductors. In many cases, these advantages allow for higher system operating frequencies and more gate capacity at a lower cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.